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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. tps62801 slvsdd1a ? december 2017 ? revised march 2018 tps62801 1.8-v to 5.5-v, 1-a, 2.3- a i q step down converter in a 6-pin, 0.35-mm pitch wcsp package 1 1 features 1 ? input voltage range from 1.8 v to 5.5 v ? 2.3- a operating quiescent current ? up to 4 mhz switching frequency ? output current 1 a ? 1% output voltage accuracy ? selectable power save / forced pwm mode ? r2d converter for flexible v out setting ? 16 selectable + 1 fixed output voltages ? tps62801: 0.8v to 1.55v in 50mv steps ? smart enable pin ? optimized pinout to support 0201 components ? dcs-control ? topology ? output discharge ? 100% duty cycle operation ? tiny 6-pin, 0.35 mm pitch wcsp package ? supports < 0.6 mm solution height 2 applications ? wearable electronic ? smart phones ? iot applications ? 2xaa battery powered applications 3 description the tps6280x device family is a step down converter with 2.3- a typical quiescent current featuring highest efficiency and smallest solution size. ti ' s dcs-control ? topology enables the device to operate with tiny inductors and capacitors up to a 4 mhz switching frequency. at light load conditions, it seamlessly enters power save mode to reduce switching cycles and maintaining high efficiency. connecting the vsel/mode pin to gnd selects a 1.2-v fixed output voltage. with only one external resistor connected to vsel/mode pin, 16 internally set output voltages can be selected. an integrated r2d (resistor to digital) converter reads out the external resistor and sets the output voltage. the same device part number can be used for different applications and voltage rails just by changing a single resistor. furthermore, the internally set output voltage provides better accuracy compared to a traditional external resistor divider network. once the device has started up, the dc/dc converter enters forced pwm mode by applying a high level at the vsel/mode pin. in this operating mode, the device runs at typically 4-mhz switch frequency enabling lowest output voltage ripple. the tps6280x device series comes in a tiny 6-pin wcsp package with 0.35-mm pitch. device information (1) part number package body size (nom) tps6280x dsbga (6) 1.05 mm 0.70 mm x 0.4mm (1) for all available packages, see the orderable addendum at the end of the datasheet. sp sp typical application efficiency vs. iout @ 1.2 v v out iout [ma ] efficiency % 0.001 0.01 0.1 1 10 100 1000 40 45 50 55 60 65 70 75 80 85 90 95 slvs v in = 1.8v v in = 2.5v v in = 3.3v v in = 3.6v v in = 4.2v v in = 5.0v pfm pwm gnd l = 0.47 h m vos vsel /mode sw vin v 1.8v - 5.5v in c4.7 in m f c 10 f out m tps62801 en r vsel 16 selectable v0.8v - 1.55v out off on gnd l = 0.47 h m vos vsel /mode sw vin v 1.8v - 5.5v in c4.7 in m f c 10 f out m tps62801 en 1.2v fixed v out off on tools & software technical documents ordernow productfolder support &community
2 tps62801 slvsdd1a ? december 2017 ? revised march 2018 www.ti.com product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 device comparison table ..................................... 3 6 pin configuration and functions ......................... 3 7 specifications ......................................................... 5 7.1 absolute maximum ratings ..................................... 5 7.2 esd ratings .............................................................. 5 7.3 recommended operating conditions ....................... 5 7.4 thermal information .................................................. 6 7.5 electrical characteristics ........................................... 6 7.6 typical characteristics .............................................. 8 8 detailed description ............................................ 10 8.1 overview ................................................................. 10 8.2 functional block diagram ....................................... 10 8.3 feature description ................................................. 10 8.4 device functional modes ........................................ 13 9 application and implementation ........................ 14 9.1 application information ............................................ 14 9.2 typical application ................................................. 14 9.3 system examples ................................................... 24 10 power supply recommendations ..................... 25 11 layout ................................................................... 25 11.1 layout guidelines ................................................. 25 11.2 layout example .................................................... 25 12 device and documentation support ................. 26 12.1 device support ...................................................... 26 12.2 community resources .......................................... 26 12.3 trademarks ........................................................... 26 12.4 electrostatic discharge caution ............................ 26 12.5 glossary ................................................................ 26 13 mechanical, packaging, and orderable information ........................................................... 26 13.1 chip scale package dimensions .......................... 26 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from original (december 2017) to revision a page ? production data release ........................................................................................................................................................ 1
3 tps62801 www.ti.com slvsdd1a ? december 2017 ? revised march 2018 product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) planned device options, in development 5 device comparison table device function vsel/mode fixed vout selectable output voltages with r vsel f sw [mhz] i out [a] soft start t ss output discharge tps62801 vsel + mode 1.20v (vsel / mode = gnd) 0.8v - 1.55v in 50mv steps 4 1 125 s yes tps62802 (1) vsel + mode 1.8v (vsel / mode = gnd) 1.8v - 3.3v in 100mv steps 4 1 400 s yes 6 pin configuration and functions yka package 6-pin dsbga pin functions pin i/o description name no. gnd a1 pwr gnd supply pin. connect this pin close to the gnd terminal of the input and output capacitor. vin b1 pwr v in power supply pin. connect the input capacitor close to this pin for best noise and voltage spike suppression. a ceramic capacitor of 4.7 f is required. vsel/mode c1 in this pin has two functions depending on the device option: digital input only, or r2d converter + digital input. connecting a resistor selects a pre defined output voltage. once the device has started up, the r2d converter is disabled and the pin operates as an input. applying a high level selects forced pwm mode operation, a low level power save mode operation. for the fixed output voltage options, this pin operates as input only to select between power save mode and forced pwm mode. vos a2 in output voltage sense pin for the internal feedback divider network and regulation loop. this pin also discharges v out when the converter is disabled by an internal mosfet. connect this pin directly to the output capacitor with a short trace. sw b2 out the switch pin is connected to the internal mosfet switches. connect the inductor to this terminal. en c2 in high level enables the devices, low level turns the device off. the pin features an internal pulldown resistor, which is disabled once the device has started up. gnd vin vsel/ mode sw vos en a b c 1 2 top view gnd vin vsel/ mode sw vos en 2 1 bottom view a b c
4 tps62801 slvsdd1a ? december 2017 ? revised march 2018 www.ti.com product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) planned device options table 1. output voltage setting (vsel/mode pin) output voltage setting v out [v] r vsel resistance [k ], e96 resistor series, 1% accuracy, temperature coefficient better or equal +/-200ppm/ c tps62801 tps62802 (1) 1.2 1.8 connected to gnd (no resistor needed) 0.8 1.8 10.0 0.85 1.9 12.1 0.9 2.0 15.4 0.95 2.1 18.7 1.0 2.2 23.7 1.05 2.3 28.7 1.1 2.4 36.5 1.15 2.5 44.2 1.2 2.6 56.2 1.25 2.7 68.1 1.3 2.8 86.6 1.35 2.9 105.0 1.4 3.0 133.0 1.45 3.1 162.0 1.5 3.2 205.0 1.55 3.3 249.0 or larger
5 tps62801 www.ti.com slvsdd1a ? december 2017 ? revised march 2018 product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute ? maximum ? rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground terminal gnd. (3) while switching 7 specifications 7.1 absolute maximum ratings (1) min max unit pin voltage (2) vin ? 0.3 6 v sw (dc) ? 0.3 v in +0.3v v sw (ac), less than 10ns (3) ? 2.5 9 v en, vsel/mode ? 0.3 6 v vos ? 0.3 5 v operating junction temperature, t j ? 40 150 c storage temperature, t stg ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. the human body model is a 100-pf capacitor discharged through a 1.5-k resistor into each pin. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 7.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001, all pins (1) 2000 v charged device model (cdm), per jedec specification jesd22-c101, all pins (2) 500 (1) depending on thermal performance of pcb, maximum output current may be reduced. 7.3 recommended operating conditions min nom max unit v in supply voltage v in 1.8 5.5 v i out output current, v in > /= 2.3v (1) 1 a output current, v in < 2.3v (1) 0.7 l effective inductance 0.19 0.82 h c out effective output capacitance 3 26 f c in effective input capacitance 0.5 4.7 f c vsel/ mode external parasitic capacitance at vsel/mode pin 30 pf r vsel resistance range for external resistor at vsel/mode pin (e96 1% resistor values) 10 249 k ? external resistor tolerance e96 series at vsel/mode pin 1% e96 resistor series temperature coefficient (tcr) -200 +200 ppm/ c t j operating junction temperature range -40 125 c
6 tps62801 slvsdd1a ? december 2017 ? revised march 2018 www.ti.com product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 7.4 thermal information thermal metric (1) tps6280x unit yka (dsbga) 6 pins r ja junction-to-ambient thermal resistance 147.7 c/w r jc(top) junction-to-case (top) thermal resistance 1.7 c/w r jb junction-to-board thermal resistance 47.5 c/w jt junction-to-top characterization parameter 0.5 c/w jb junction-to-board characterization parameter 47.6 c/w r jc(bot) junction-to-case (bottom) thermal resistance ? c/w 7.5 electrical characteristics v in = 3.6 v, t j = ? 40 c to 125 c typical values are at t a = 25 c (unless otherwise noted) parameter test conditions min typ max unit supply i q operating quiescent current (power save mode) en = v in , vsel/mode = gnd, i out = 0 a, v out = 1.2 v, device not switching, t j = -40 c to +85 c 2.3 4 a en = v in , vsel/mode = gnd, i out = 0 a, v out = 1.2 v, device switching 2.5 a operating quiescent current (pwm mode) en = v in , vsel/mode = v in (after power up), device switching, i out = 0ma, v out = 1.2v 8 ma i sd shutdown current en = gnd, shutdown current into vin, vsel/mode = gnd, t j = -40 c to +85 c 120 250 na v th_ uvlo+ undervoltage lockout threshold rising v in 1.65 1.8 v v th_uvlo ? falling v in 1.56 1.7 v input en v ih th high level input voltage 0.8 v v il th low level input voltage 0.4 v i in input bias current t j = -40 c to +85 c, en = high 10 25 na r pd internal pulldown resistance en = low 500 k input vsel/mode v ih th high level input voltage 0.8 v v il th low level input voltage 0.4 v i in input bias current en = high, t j = -40 c to +85 10 25 na power switches i lkg_sw leakage current into sw pin v sw = 1.2v, t j = -40 c to +85 c 10 25 na r ds(on) high side mosfet on- resistance i out = 500 ma 120 170 m low side mosfet on- resistance i out = 500 ma 80 115 m i limf high side mosfet switch current limit 1.2 1.4 1.6 a low side mosfet switch current limit 1.1 1.3 1.5 a output voltage discharge r dsch_vos mosfet on-resistance en = gnd, i vos = ? 10 ma into vos pin, t j = -40 c to +85 c 7 11 i in_vos bias current into vos pin en = v in , v out = 1.2 v (internal 12m resistor divider), t j = -40 c to +85 c 100 400 na
7 tps62801 www.ti.com slvsdd1a ? december 2017 ? revised march 2018 product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated electrical characteristics (continued) v in = 3.6 v, t j = ? 40 c to 125 c typical values are at t a = 25 c (unless otherwise noted) parameter test conditions min typ max unit thermal protection t sd thermal shutdown temperature rising junction temperature, pwm mode 160 c thermal shutdown hysteresis 20 c output v out output voltage range tps62801, 50mv steps 0.8 1.55 v v out output voltage range tps62802, 100mv steps 1.8 3.3 v v out output voltage accuracy power save mode 0% v out output voltage accuracy pwm mode, i out = 0 ma, t j = 25 c to +85 c -1% 0% 1% v out output voltage accuracy pwm mode, i out = 0 ma, t j = -40 c to +125 c -2% 0% 1.7% v out dc output voltage load regulation 0.1 %/a v out dc output voltage line regulation 0 %/v t onmin minimum on time v in = 3.6v, v out = 1.2v 85 ns t onmin minimum on time v in = 3.6v, v out = 1.8v, 100 120 140 ns t offmin minimum off time 40 ns f sw switching frequency v in = 3.6v, v out = 1.2v, pwm operation 4 mhz t startup_delay regulator start up delay time from en = low to high until device starts switching, fixed output voltage options 220 850 s t startup_delay regulator start up delay time from en = low to high until device starts switching, tps62801, r vsel = 249k 500 1100 s t ss soft start time tps62801, from v out = 0v to 95% of v out nominal, 125 170 s t ss soft start time tps62802, from v out = 0v to 95% of v out nominal 400 500 s
8 tps62801 slvsdd1a ? december 2017 ? revised march 2018 www.ti.com product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 7.6 typical characteristics figure 1. shutdown current i sd device not switching figure 2. quiescent current i q v in falling device switching, no load, v out = 1.2v en = v in vsel/mode = gnd figure 3. operating quiescent current i q v in rising device switching, no load, v out = 1.2v en = v in vsel/mode = gnd figure 4. operating quiescent current i q figure 5. high side switch drain source resistance r ds(on) figure 6. low side switch drain source resistance r ds(on) v in [v] i sd [ a] m 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 t j = -40c t j = -10c t j = 30c t j = 85c t j = 125c v in [v] i q [ a] m 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 t j = -40c t j = -10c t j = 30c t j = 85c t j = 125c v in [v] i q [ a] m 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 t j = -40c t j = 25c t j = 85c v in [v] i q [ a] m 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0.1 1 10 100 1000 t j = -40c t j = 25c t j = 85c v in [v] r ds(on) [m : w ] 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0 25 50 75 100 125 150 175 200 t j = -40c t j = -10c t j = 30c t j = 85c t j = 125c v in [v] r ds(on) [m : w ] 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 t j = -40c t j = -10c t j = 30c t j = 85c t j = 125c
9 tps62801 www.ti.com slvsdd1a ? december 2017 ? revised march 2018 product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated typical characteristics (continued) figure 7. vos discharge switch drain source resistance r dsch_vos v in [v] r dsch_vos [ w ] 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0 2 4 6 8 10 12 14 16 18 20 t j = -40c t j = -10c t j = 30c t j = 85c t j = 125c
10 tps62801 slvsdd1a ? december 2017 ? revised march 2018 www.ti.com product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 8 detailed description 8.1 overview the tps6280x is a high frequency synchronous step down converter with ultra low quiescent current consumption. using ti's dcs-control ? topology, the device extends the high efficiency operation area down to microamperes of load current during power save mode operation. ti's dcs-control ? (direct control with seamless transition into power save mode) is an advanced regulation topology, which combines the advantages of hysteretic and voltage mode control. characteristics of dcs-control ? are excellent ac load regulation and transient response, low output ripple voltage and a seamless transition between pfm and pwm mode operation. dcs-control ? includes an ac loop which senses the output voltage (vos pin) and directly feeds the information to a fast comparator stage. this comparator sets the switching frequency, which is constant for steady state operating conditions, and provides immediate response to dynamic load changes. in order to achieve accurate dc load regulation, a voltage feedback loop is used. the internally compensated regulation network achieves fast and stable operation with small external components and low esr capacitors. 8.2 functional block diagram 8.3 feature description 8.3.1 smart enable and shutdown (en) an internal 500k resistor pulls the en pin to gnd and avoids the pin to be floating. this prevents an uncontrolled start up of the device in case the en pin cannot be driven to low level safely. with en low, the device is in shutdown mode. the device is turned on with en set to a high level. the pulldown control circuit disconnects the pulldown resistor on the en pin once the internal control logic and the reference have been powered up successfully. with en set to a low level the device enters shutdown mode and the pulldown resistor is activated again. uvloen gate driver current limit comparator sw limithigh side vingnd pmos nmos control logic vos v fb main comparator direct control error amplifier t on timer vin vos dcs control current limit comparator limitlow side power stage vos vsel/ mode v discharge out en v ref ramp uvlo thermal shutdown smart enable r2d converter power save / forced pwm mode operation ultra low power 0.4v v ref internal feedback divider network v fb vos softstart timing* startup delay * pulldown control input buffer 500k w resitor to digital converter
11 tps62801 www.ti.com slvsdd1a ? december 2017 ? revised march 2018 product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated feature description (continued) 8.3.2 softstart once the device has been enabled with en high, it initializes and powers up its internal circuits. this occurs during the regulator start up delay time t startup_delay . once t startup_delay expires, the internal soft start circuitry ramps up the output voltage within the soft start time t ss . figure 8. device startup 8.3.3 vsel/mode pin this pin has multiple functions, depending on the device option. see table. in device options with only one fixed output voltage, the r2d function is disabled and the pin just operates as a digital input for mode selection. 8.3.3.1 output voltage selection (r2d converter) the output voltage is set with a single external resistor connected between the vsel/mode pin and gnd. once the device has been enabled and the control logic as well the internal reference has been powered up, a r2d (resistor to digital) conversion is started to detect the external resistor r vsel . an internal current source applies current through the external resistor and an internal adc reads back the resulting voltage level. depending on the level, an internal feedback divider network is selected to set the correct output voltage. once this r2d conversion is finished within the regulator start up delay time t startup_delay , the current source is turned off to avoid current flow through the external resistor. after power up, the pin is configured as an input for mode selection. therefore, the output voltage is set only once. if the mode selection function is used in combination with the vsel function, ensure that there is no additional current path or capacitance greater than 30pf total to gnd, during r2d conversion. otherwise the additional current to gnd is interpreted as a lower resistor value and a false output voltage will be set. table 1 lists the correct resistor values for r vsel to set the appropriate output voltages. the r2d converter is designed to operate with resistor values out of the e96 table and requires 1% resistor value accuracy. ensure that there is no other leakage path than the r vsel resistor at the vsel/mode pin during an undervoltage lockout event. otherwise a false voltage will be set. connecting vsel/mode to gnd selects a pre-defined output voltage (tps62801 = 1.2v, tps62802 = 1.8v). in this case, no external resistor is needed and enables a smaller solution size. 8.3.3.2 mode selection: power save mode / forced pwm operation a low level at this pin selects power save mode operation, and a high level selects forced pwm operation. the mode can be changed during operation after the device has been powered up. in device options with output voltage selection (vsel) function (tps62801, tps62802), the mode selection function is only available after the r2d converter has read out the external resistor. t ss t startup_delay en device starts switchingand ramps v out v out
12 tps62801 slvsdd1a ? december 2017 ? revised march 2018 www.ti.com product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated feature description (continued) 8.3.4 undervoltage lockout (uvlo) to avoid misoperation of the device at low input voltages, an undervoltage lockout (uvlo) comparator monitors the supply voltage. the uvlo comparator shuts down the device at an input voltage of 1.7v (max) with falling v in . the device starts at an input voltage of 1.8v (max) rising v in . once the device re-enters operation out of an undervoltage lockout condition, it behaves like being enabled. the internal control logic is powered up and the external resistor at the vsel/mode pin is read out. 8.3.5 switch current limit / short circuit protection the tps6280x integrates a current limit on the high side, as well on the low side mosfets to protect the device against overload or short circuit conditions. the current in the switches is monitored cycle by cycle. if the high side mosfet current limit i limf trips, the high side mosfet is turned off and the low side mosfet is turned on to ramp down the inductor current. once the inductor current through the low side switch decreases below the low side mosfet current limit i limf , the low side mosfet is turned off and the high side mosfet turns on again. 8.3.6 thermal shutdown the junction temperature (t j ) of the device is monitored by an internal temperature sensor. if t j exceeds the thermal shutdown temperature t sd of 160 c (typ), the device enters thermal shutdown. both the high side and low side power fets are turned off. when t j decreases below the hysteresis amount of typically 20 c, the converter resumes normal operation, beginning with a soft start. the thermal shutdown is not active in power save mode. 8.3.7 output voltage discharge the purpose of the output discharge function is to ensure a defined down-ramp of the output voltage when the device is disabled and to keep the output voltage close to 0 v. the output discharge feature is only active once the device has been enabled at least once since the supply voltage was applied. the output discharge function is not active if the device is disabled and the supply voltage is applied the first time. the internal discharge resistor is connected to the vos pin. the discharge function is enabled as soon as the device is disabled. the minimum supply voltage required to keep the discharge function active is v in > v th_uvlo- .
13 tps62801 www.ti.com slvsdd1a ? december 2017 ? revised march 2018 product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 8.4 device functional modes 8.4.1 power save mode operation the dcs-control ? topology supports power save mode operation. at light loads the device operates in pfm (pulse frequency modulation) mode that generates a single switching pulse to ramp up the inductor current and recharge the output capacitor, followed by a sleep period where most of the internal circuits are shutdown to achieve lowest operating quiescent current. during this time, the load current is supported by the output capacitor. the duration of the sleep period depends on the load current and the inductor peak current. during the sleep periods, the current consumption is reduced to typically 2.3 a. this low quiescent current consumption is achieved by an ultra low power voltage reference, an integrated high impedance feedback divider network and an optimized power save mode operation. in pfm mode, the switching frequency varies linearly with the load current. at medium and high load conditions, the device enters automatically pwm (pulse width modulation) mode and operates in continuous conduction mode with a nominal switch frequency f sw of typically 4mhz. the switching frequency in pwm mode is controlled and depends on v in and v out . the boundary between pwm and pfm mode is when the inductor current becomes discontinuous. if the load current decreases, the converter seamlessly enters pfm mode to maintain high efficiency down to very light loads. since dcs-control ? supports both operation modes within one single building block, the transition from pwm to pfm mode is seamless with minimum output voltage ripple. 8.4.2 forced pwm mode operation after the device has powered up and ramped up v out , the vsel/mode pin acts as an input. with a high level on vsel/mode pin, the device enters forced pwm mode and operates with a constant switching frequency over the entire load range, even at very light loads. this reduces or eliminates interference with rf and noise sensitive circuits, but lowers efficiency at light loads. 8.4.3 100% mode operation the duty cycle of the buck converter operating in pwm mode is given as d = v out /v in . the duty cycle increases as the input voltage comes close to the output voltage. in 100% duty cycle mode, it keeps the high side switch on continuously. the high side switch stays turned on as long as the output voltage is below the internal set point. this allows the conversion of small input to output voltage differences.
14 tps62801 slvsdd1a ? december 2017 ? revised march 2018 www.ti.com product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) see third-party products disclaimer 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the following section discusses the design of the external components to complete the power supply design for several input and output voltage options by using typical applications as a reference. 9.2 typical application figure 9. tps62801 adjustable v out application circuit additional circuits are shown in the system examples section. 9.2.1 design requirements table 2 shows the list of components for the application circuit and the characteristic application curves table 2. components for application characteristic curves reference description value size [l x w x t] manufacturer (1) tps6280x step down converter 1.05mm x 0.70mm x 0.4mm max. texas instruments c in ceramic capacitor, grm155r60j475me47d 4.7 f 0402 (1mm x 0.5mm x 0.6mm max.) murata c out ceramic capacitor, grm155r60j106me15d 10 f 0402 (1mm x 0.5mm x 0.65mm max.) murata l inductor dfe18sanr47mg0l 0.47 h 0603 (1.6mm x 0.8mm x 1.0mm max.) murata (1) inductor tolerance and current de-rating is anticipated. the effective inductance can vary by 20% and -20%. (2) capacitance tolerance and bias voltage de-rating is anticipated. the effective capacitance varies by +20% and ? 50%. (3) typical application configuration. other check marks indicate alternative filter combinations. 9.2.2 detailed design procedure the inductor and output capacitor together provide a low-pass filter. to simplify this process, table 3 outlines possible inductor and capacitor value combinations. table 3. recommended lc output filter combinations inductor value [ h] (1) output capacitor value [ f] (2) 4.7 f 10 f 22 f 0.47 (3) gnd l = 0.47 h m vos vsel /mode sw vin v 1.8v - 5.5v in c4.7 in m f c 10 f out m tps62801 en r vsel 16 selectable v0.8v - 1.55v out off on pfm pwm
15 tps62801 www.ti.com slvsdd1a ? december 2017 ? revised march 2018 product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) see third-party products disclaimer 9.2.2.1 inductor selection the inductor value affects the peak-to-peak ripple current, the pwm-to-pfm transition point, the output voltage ripple and the efficiency. the selected inductor has to be rated for its dc resistance and saturation current. the inductor ripple current ( i l ) decreases with higher inductance and increases with higher v in or v out and can be estimated according to equation 1 . equation 2 calculates the maximum inductor current under static load conditions. the saturation current of the inductor should be rated higher than the maximum inductor current, as calculated with equation 2 . this is recommended because during a heavy load transient the inductor current rises above the calculated value. a more conservative way is to select the inductor saturation current according to the high side mosfet switch current limit, i limf . (1) where ? f = switching frequency ? l = inductor value ? i l = peak to peak inductor ripple current ? i lmax = maximum inductor current (2) the table below shows a list of possible inductors. table 4. list of possible inductors (1) inductance [ h] inductor type size imperial (metric) dimensions l x w x t supplier (1) 0.47 dfe18san_g0 0603 (1608) 1.6mm x 0.8mm x 1.0mm max murata 0.47 hteb16080f 0603 (1608) 1.6mm x 0.8mm x 0.6mm max. cyntec 0.47 htet1005fe 0402 (1005) 1.0mm x 0.5mm x 0.65mm max. cyntec 0.47 tfm160808alc 0603 (1608) 1.6mm x 0.8mm x 0.8mm max. tdk 9.2.2.2 output capacitor selection the dcs-control ? scheme of the tps6280x allows the use of tiny ceramic capacitors. ceramic capacitors with low esr values have the lowest output voltage ripple and are recommended. the output capacitor requires either an x7r or x5r dielectric. at light load currents, the converter operates in power save mode and the output voltage ripple is dependent on the output capacitor value. a larger output capacitors can be used reducing the output voltage ripple. l vout 1 vin i = vout l - d | l lmax outmax i i = i + 2 d
16 tps62801 slvsdd1a ? december 2017 ? revised march 2018 www.ti.com product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) see third-party products disclaimer 9.2.2.3 input capacitor selection because the buck converter has a pulsating input current, a low esr input capacitor is required for best input voltage filtering to minimize input voltage spikes. for most applications a 4.7- f input capacitor is sufficient. when operating from a high impedance source, a larger input buffer capacitor is recommended avoiding voltage drops during start-up and load transients. the input capacitor can be increased without any limit for better input voltage filtering. table 5 shows a selection of input and output capacitors. table 5. list of possible capacitors (1) capacitance [ f] capacitor type size imperial (metric) dimensions l x w x t supplier (1) 4.7 grm155r60j475me47d 0402 (1005) 1.0mm x 0.5mm x 0.6mm max. murata 4.7 grm035r60j475me15 0201(0603) 0.6mm x 0.3mm x 0.55mm max murata 10 grm155r60j106me15d 0402 (1005) 1.0mm x 0.5mm x 0.65mm max. murata
17 tps62801 www.ti.com slvsdd1a ? december 2017 ? revised march 2018 product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 9.2.3 application curves the conditions for below application curves are v in = 3.6 v, v out = 1.2 v and the components listed in table 2 , unless otherwise noted. tps62801 r vsel = 10 k to gnd figure 10. efficiency power save mode v out = 0.8 v tps62801 r vsel = 15.4 k to gnd figure 11. efficiency power save mode v out = 0.9 v tps62801 r vsel = 56.2 k , vsel/mode pin = high after startup figure 12. efficiency forced pwm mode v out = 1.2 v tps62801 vsel/mode = gnd figure 13. efficiency power save mode v out = 1.2 v tps62802 vsel/mode = gnd figure 14. efficiency power save mode v out = 1.8 v tps62801 vsel/mode = gnd v out = 1.2 v pfm/pwm mode t j = 25 c figure 15. output voltage vs. output current iout [ma ] efficiency % 0.001 0.01 0.1 1 10 100 1000 40 45 50 55 60 65 70 75 80 85 90 95 slvs v in = 1.8v v in = 2.5v v in = 3.3v v in = 3.6v v in = 4.2v v in = 5.0v iout [ma ] efficiency % 1 10 100 1000 0 10 20 30 40 50 60 70 80 90 slvs v in = 1.8v v in = 2.5v v in = 3.3v v in = 3.6v v in = 4.2v v in = 5.0v i out [ma ] efficiency % 0.001 0.01 0.1 1 10 100 1000 40 45 50 55 60 65 70 75 80 85 90 95 100 slvs v in = 2.5v v in = 3.3v v in = 3.6v v in = 4.2v v in = 5.0v i out [ma ] v out [v] 0.01 0.1 1 10 100 1000 1.164 1.176 1.188 1.200 1.212 1.224 1.236 1.248 t j = 25c slvs v in = 1.8v v in = 2.5v v in = 3.3v v in = 3.6v v in = 4.2v v in = 5.0v i out [ma] efficiency % 0.001 0.01 0.1 1 10 100 1000 40 45 50 55 60 65 70 75 80 85 90 95 slvs v in = 2.3v v in = 2.7v v in = 3.7v v in = 4.2v v in = 5.0v i out [ma ] efficiency % 0.001 0.01 0.1 1 10 100 1000 40 45 50 55 60 65 70 75 80 85 90 95 slvs v in = 1.8v v in = 2.6v v in = 3.6v v in = 4.2v v in = 5.0v
18 tps62801 slvsdd1a ? december 2017 ? revised march 2018 www.ti.com product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated tps62801 vsel/mode = gnd v out = 1.2 v pfm/pwm mode t j = ? 40 c figure 16. output voltage vs. output current tps62801 vsel/mode = gnd v out = 1.2 v pfm/pwm mode t j = 85 c figure 17. output voltage vs. output current tps62801 vsel/mode = high after startup v out = 1.2 v forced pwm mode t j = 25 c figure 18. output voltage vs. output current tps62801 vsel/mode = high after startup v out = 1.2 v forced pwm mode t j = ? 40 c figure 19. output voltage vs. output current tps62801 vsel/mode = high after startup v out = 1.2 v forced pwm mode t j = 85 c figure 20. output voltage vs. output current tps62801 vsel/mode = gnd v out = 1.2 v pfm/pwm mode t j = 25 c figure 21. switching frequency vs. output current i out [ma] switching frequency [khz] 0 100 200 300 400 500 600 700 800 900 1000 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 slvsslvs v in = 1.8v v in = 2.5v v in = 3.3v v in = 3.6v v in = 4.2v v in = 5.0v i out [ma ] v out [v] 0.01 0.1 1 10 100 1000 1.188 1.200 1.212 t j = -40c slvs v in = 1.8v v in = 2.5v v in = 3.3v v in = 3.6v v in = 4.2v v in = 5.0v i out [ma ] v out [v] 0.01 0.1 1 10 100 1000 1.188 1.200 1.212 t j = 25c slvs v in = 1.8v v in = 2.5v v in = 3.3v v in = 3.6v v in = 4.2v v in = 5.0v i out [ma ] v out [v] 0.01 0.1 1 10 100 1000 1.164 1.176 1.188 1.200 1.212 1.224 1.236 1.248 t j = -40c slvs v in = 1.8v v in = 2.5v v in = 3.3v v in = 3.6v v in = 4.2v v in = 5.0v i out [ma ] v out [v] 0.01 0.1 1 10 100 1000 1.164 1.176 1.188 1.200 1.212 1.224 1.236 1.248 t j = 85c slvs v in = 1.8v v in = 2.5v v in = 3.3v v in = 3.6v v in = 4.2v v in = 5.0v i out [ma ] v out [v] 0.01 0.1 1 10 100 1000 1.188 1.200 1.212 t j = 85c slvs v in = 1.8v v in = 2.5v v in = 3.3v v in = 3.6v v in = 4.2v v in = 5.0v
19 tps62801 www.ti.com slvsdd1a ? december 2017 ? revised march 2018 product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated tps62801 vsel/mode = gnd v out = 1.2 v pfm/pwm mode t j = 25 c figure 22. switching frequency (zoom in) tps62801 vsel/mode = high after startup v out = 1.2 v forced pwm mode t j = 25 c figure 23. switching frequency vs. output current tps62801 vsel/mode = 10 k to gnd v out = 0.8 v pfm/pwm mode t j = 25 c figure 24. switching frequency vs. output current tps62801 v out = 1.2 v vsel/mode = gnd i out = 25 a pfm mode figure 25. typical operation power save mode i out [ma] switching frequency [khz] 0 100 200 300 400 500 600 700 800 900 1000 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 slvsslvs v in = 1.8v v in = 2.5v v in = 3.3v v in = 3.6v v in = 4.2v v in = 5.0v i out [ma] switching frequency [khz] 0 1 2 3 4 5 6 7 8 9 10 0 10 20 30 40 50 60 70 80 90 100 slvsslvs v in = 1.8v v in = 2.5v v in = 3.3v v in = 3.6v v in = 4.2v v in = 5.0v i out [ma] switching frequency [khz] 0 100 200 300 400 500 600 700 800 900 1000 0 500 1000 1500 2000 2500 3000 3500 4000 4500 slvs v in = 1.8v v in = 3.6v v in = 4.2v v in = 5.0v
20 tps62801 slvsdd1a ? december 2017 ? revised march 2018 www.ti.com product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated tps62801 v out = 1.2 v vsel/mode = gnd i out = 10 ma pfm mode figure 26. typical operation power save mode tps62801 v out = 1.2 v vsel/mode = gnd i out = 500 ma pwm mode figure 27. typical operation pwm mode tps62801 v out = 1.2 v i out = 0 ma forced pwm mode vsel/mode = vin (after startup) figure 28. typical operation forced pwm mode tps62801 v out = 1.2 v vsel/mode = gnd rise / fall time < 1 s i out = 0 ma to 50 ma, pfm mode figure 29. load transient power save mode
21 tps62801 www.ti.com slvsdd1a ? december 2017 ? revised march 2018 product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated tps62801 v out = 1.2 v vsel/mode = gnd rise / fall time < 1 s pfm / pwm mode i out = 5 ma to 500 ma figure 30. load transient power save mode tps62801 v out = 1.2 v vsel/mode = vin rise / fall time < 1 s (after startup) forced pwm mode i out = 5 ma to 500 ma figure 31. load transient forced pwm mode tps62801 v out = 1.2 v vsel/mode = gnd i out = 1 ma to 1 a 1 khz pfm/pwm mode figure 32. ac load sweep power save mode tps62801 v out = 1.2 v vsel/mode = vin i out = 1 ma to 1 a, 1 khz (after start up) forced pwm mode figure 33. ac load sweep forced pwm mode
22 tps62801 slvsdd1a ? december 2017 ? revised march 2018 www.ti.com product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated tps62801 v out = 1.2 v v in = 3.6 v to 4.2 v rise / fall time = 10 s i out = 50 ma figure 34. line transient pfm mode tps62801 v out = 1.2 v v in = 3.6 v to 4.2 v rise / fall time = 10 s i out = 500 ma figure 35. line transient pwm mode tps62801 v out = 0.8 v vsel/mode = low r vsel = 10 k (via r vsel ) r load = 220 figure 36. start up v out = 0.8 v tps62801 v out = 1.2 v vsel/mode = gnd r load = 220 figure 37. start up v out = 1.2 v
23 tps62801 www.ti.com slvsdd1a ? december 2017 ? revised march 2018 product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated tps62801 v out = 1.55 v vsel/mode = low r vsel = 249 k (via r vsel ) r load = 220 figure 38. start up v out = 1.55 v tps62801 v out = 1.2 v vsel/mode = v in en = high to low no load figure 39. output discharge
24 tps62801 slvsdd1a ? december 2017 ? revised march 2018 www.ti.com product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 9.3 system examples this section shows additional circuits for various output voltages. figure 40. tps62801 vsel connected to gnd for 1.2v fixed v out figure 41. tps62801 adjustable v out application circuit figure 42. tps62802 adjustable v out application circuit figure 43. tps62802 vsel connected to gnd for 1.8v fixed v out gnd l = 0.47 h m vos sw vin v up to 5.5v in c4.7 in m f c out tps62802 en r vsel 16 selectable v1.8v - 3.3v out off on pfm pwm vsel /mode gnd l = 0.47 h m vos sw vin v 1.8v - 5.5v in c4.7 in m f c 10 f out m tps62801 en 1.2v fixed off on vsel /mode copyright ? 2017, texas instruments incorporated gnd l = 0.47 h m vos sw vin v 1.8v - 5.5v in c4.7 in m f c 10 f out m tps62802 en 1.8v fixed off on vsel /mode copyright ? 2017, texas instruments incorporated gnd l = 0.47 h m vos vsel /mode sw vin v 1.8v - 5.5v in c4.7 in m f c 10 f out m tps62801 en r vsel 16 selectable v0.8v - 1.55v out off on pfm pwm
25 tps62801 www.ti.com slvsdd1a ? december 2017 ? revised march 2018 product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 10 power supply recommendations the power supply must provide a current rating according to the supply voltage, output voltage and output current of the tps6280x. 11 layout 11.1 layout guidelines ? as for all switching power supplies, the layout is an important step in the design. care must be taken in board layout to get the specified performance. ? it is critical to provide a low inductance, low impedance ground path. therefore, use wide and short traces for the main current paths. ? the input capacitor should be placed as close as possible to the ic's vin and gnd pins. this is the most critical component placement. ? the vos line is a sensitive, high impedance line and should be connected to the output capacitor and routed away from noisy components and traces (e.g. sw line) or other noise sources. 11.2 layout example figure 44. pcb layout example c out c in l ic
26 tps62801 slvsdd1a ? december 2017 ? revised march 2018 www.ti.com product folder links: tps62801 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 12 device and documentation support 12.1 device support 12.1.1 third-party products disclaimer ti's publication of information regarding third-party products or services does not constitute an endorsement regarding the suitability of such products or services or a warranty, representation or endorsement of such products or services, either alone or in combination with any ti product or service. 12.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.3 trademarks dcs-control, e2e are trademarks of texas instruments. topology is a trademark of others. 12.4 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. 13.1 chip scale package dimensions the tps62801 device is available in a 6-bump chip scale package (dsbga). see the attached package drawing. the yka package d and e dimensions are given as: d e 1054 m 30 m 704 m 30 m
package option addendum www.ti.com 16-mar-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples TPS62801YKAR active dsbga yka 6 3000 green (rohs & no sb/br) sac396 level-1-260c-unlim -40 to 125 + tps62801ykat active dsbga yka 6 250 green (rohs & no sb/br) sac396 level-1-260c-unlim -40 to 125 + (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 16-mar-2018 addendum-page 2
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TPS62801YKAR dsbga yka 6 3000 178.0 8.4 0.81 1.16 0.46 4.0 8.0 q1 tps62801ykat dsbga yka 6 250 178.0 8.4 0.81 1.16 0.46 4.0 8.0 q1 package materials information www.ti.com 9-mar-2018 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TPS62801YKAR dsbga yka 6 3000 220.0 220.0 35.0 tps62801ykat dsbga yka 6 250 220.0 220.0 35.0 package materials information www.ti.com 9-mar-2018 pack materials-page 2
www.ti.com package outline c 0.4 max 0.18 0.13 0.35 typ 6x 0.24 0.19 0.35 typ 0.7 typ b e a d 4223607/a 03/2017 dsbga - 0.4 mm max height yka0006 die size ball grid array notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. nanofree tm package configuration. nanofree is a trademark of texas instruments. ball a1 index area seating plane ball typ 0.05 c a 1 0.015 c a b symm symm c 2 b scale 12.000
www.ti.com example board layout 6x ( 0.2) (0.35) typ (0.35) typ ( 0.2) metal 0.0325 max solder mask opening metal under solder mask ( 0.2) solder mask opening 0.0325 min 4223607/a 03/2017 dsbga - 0.4 mm max height yka0006 die size ball grid array notes: (continued) 4. final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. for more information, see texas instruments literature number snva009 (www.ti.com/lit/snva009). symm symm land pattern example exposed metal shown scale:50x 1 2 a b c non-solder mask defined solder mask details not to scale exsposed metal solder mask defined (preferred) exposed metal
www.ti.com example stencil design (0.35) typ (0.35) typ 6x ( 0.21) (r0.05) typ metal typ 4223607/a 03/2017 dsbga - 0.4 mm max height yka0006 die size ball grid array notes: (continued) 5. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. symm symm solder paste example based on 0.075 mm - 0.1 mm thick stencil scale:50x 1 2 a b c
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